An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and ...

This paper describes an innovative methodology that makes use of XML-based IP descriptions, including constraints information, to produce automatically synthesis, STA and formal verification tool ...

Level 3 Communications is broadening the reach of its IP VPN services, which will be available to enterprise customers through systems integrators and resellers later this summer. Level 3 made the ...

Power Management is one of the major chip design challenges amongst all the dimensions of the design cycle. It poses problems for packaging, portability, & reliability (PPR), e.g.,“high system cost of ...

An IP based development methodology for building system-on-a-chip solution is described. The methodology is illustrated through a memory centric SoC architecture template intended for streaming data ...

The search for productivity inSOC (system-on-chip) designis a search for balancebetween abstraction and automation.Greater abstractionat a step in the designflow means fewer design elementsto process.

Energy efficiency is one of the primary design metrics for heterogeneous multi-core mobile platforms, and the very real threat of dark silicon reinforces the fact that we must manage energy ...